Alan Cheng

• Plans and conducts issue examinations using extensive and specialized knowledge of engineering and valuation methods, practices, and investigative audit techniques to examine and resolve various tax issues of business organizations that may include extensive subsidiaries with operations of national and/or international scope
• Provides analysis and development of issues that may impact tax compliance strategy and the examination program. Collaborates in the support of the identification, development and resolution of engineering and valuation issues
• Conducts field investigations of real and personal property, as well as documentary and accounting records of complex businesses. Values property using market data, income, and cost approaches
• Collaborates with Senior Engineer, Examiners, and other specialists to provide engineering expertise for developing significant tax compliance issues, ensuring consistent application and interpretation of tax law

• Technical lead
• Led the creation of a sophisticated physical layout design flow using Cadence and Synopsys tools for Intel projects. Managed a global team of more than 20 members to handle deployment, testing, and validation processes. Offered training to Intel design teams and developed detailed documentation to improve process efficiency
• Study, Research, and Development: Chaired technical design engineering plan meetings. Conducted thorough studies and research to identify optimal solutions and generated benchmark comparison testing reports. Presented the Physical Design Flow development plan at technical design meetings, offering recommendations for countermeasures within the design flow. Ensured compliance with design standards, guidelines, and practices throughout the execution of the layout design cycle
• Analog & Mixed Signal and Digital: Implemented the Physical Design Flow for projects utilizing Intel 22nm, 20nm, 14nm, 10nm, 7nm, and 18A, as well as TSMC process nodes. Used Intel's internal layout tool, Cadence Virtuoso, and Synopsys Fusion Compiler-based place and route flows.
• Quality: Built and maintained regression infrastructure for Analog (APR, aAPR) and Digital (RTL2GDS) APR Flows, ensuring Intel signoff quality. Established nightly validations and speedy issue resolution mechanisms
• Support & Training: Led weekly user and vendor forums for quick consultations and bug fixes. Developed post-processing scripts and checkers for software installations. Ensured automatic collaboration setup. Served as primary training instructor globally
• Documentation and Turnover: Prepared technical documents, including setup procedures, usage information, and training materials. Defined release requirements, verified validation, and assigned ownership for design processes. Authored training documents and created user guides and BKM on the wiki for the layout domain
• Accomplishments: Developed a robust regression system that ensured maximum quality coverage and release stability for customers. Optimized TFM, resulting in productivity improvements across various ranges, from 20% to 2x, significantly reducing design convergence turnaround time. Successfully managed ungated tape-ins with timely critical support. Frequently recognized with DRA awards by both current and customer organizations

o Development: Project Design Automation Engineer (PDAE) for multiple Intel design process projects. Established a Unified Design Environment for designers, which included developing an infrastructure setup for CAD TOOL configuration, as well as synchronized system for managed design libraries, and their virtual mirroring across the globe.

o Vendor Engagement: Worked with multiple vendor companies such as Synopsys/Cadence and Intel Tool development teams to review design specifications. Lead technical meetings to address the design requirement with designer. Deployed and updated design tool bundle into environment, published tool release notification, and provided tool usage document on web.

o Debug and Support: Debugged and resolved customer issues and consultations. Lead weekly meetings to address and review tool issues and enhancements with developers.

o Trainings: Provided tool trainings, usage documentations, BKMs and scripts for design teams across Intel.

o Accomplishments: The design projects successfully completed within target schedule and met the standard design specifications. With the setup of unified design environment and worldwide tool update, resulted in huge cost savings and increased designer productivity.

o Environment: Created and Maintained unique Unified Environment for the custom project. The environment was comprised of supporting multiple vendors, such as Synopsys and also supporting different technologies such as TSMC.

o Design: Generated ASIC layout for Tapeout, which was verified and was provided to Synopsys custom chip.

o Support: Supported diverse groups within Intel, locally and internationally, with the automated design environments

o Training & Licensing: Managed forecasting license lifespan, budgeting, scheduled project cycle and license funds monitoring. Created training manuals, set up training classes, and presented tools usage.

o Accomplishments: Completed a custom Synopsys chip within 12 months design cycle to meet the competitive market demand.

o Owner of Validation and Verification flow

o Support: Provided designers’ support on Layout verification flows with Hercules across multiple Microprocessor projects.

o Quality: Wrote test plans, reviewed specifications with developers and established industry standard quality metrics across the flows. Vendor Tool evaluation and competitive analysis with the internal tools

o Trainings: Provided training and BKM for the projects to use the tool more effective

Accomplishment: Improved design convergence to approximately 2x

o Validation: Design, validate and evaluate engineering design flow for Pentium project. Developed testplans for Layout Synthesis flows

o Support: Layout Design Tapeout support for each release cycle.

o Development: Developed a graphical interface for layout synthesis using PERL/Shell language.

o Accomplishments: Successfully, validated and delivered projects associated with Pentium processor.

Developments:

o Designed Intel Unified Environment and implement the internal/external tool integration into the UE.

o Designed and led the implementation of on-line Help Request System (HRS) using the Remedy. Drove new support model and proliferated finished systems to the Microprocessor teams in Oregon, Santa Clara, Folsom, and Israel.

o Developed Web based GUI and scripted front-end interface to the HRS for increased ease of use for the centralized knowledge database, and faster report/statistics generation.

o Accomplishments: Unified Environment (UE) allowed intel projects to run setup in a unified way to eliminate any unexpected integration issues. Successfully created a Ticket Tracking System, that was used widely by the Microprocessor Group.