Snehal Udar
Chandler,AZ
Summary
Principal Test Technologist with a Ph.D. in Electrical & Computer Engineering and 15+ years of experience advancing ATE and SLT test hardware, socket technologies, and high-volume silicon qualification. Recognized for driving test equipment innovation from concept to global manufacturing deployment, including burn-in automation, elastomer socket qualification, and advanced HTOL flows. Proven leader in cross-functional and supplier collaboration, risk mitigation, and yield recovery, enabling multi-billion-dollar datacenter and AI/ML Silicon product portfolios. Experienced in shaping test strategies that anticipate next-generation thermal, power, and reliability challenges.
Overview
8
8
years of professional experience
Work History
Test Technologist/TPM
INTEL Corp.
05.2017 - 07.2025
- Led development and deployment of test technologies and silicon qualification programs for Intel’s datacenter Silicon products. Directed cross-functional and supplier teams to drive new test hardware and process capabilities from concept to high-volume manufacturing. Ensured risk mitigation, manufacturing readiness, and silicon quality through collaborative problem-solving and global factory integration.
- Defined and led the strategic roadmap for Intel’s next-generation ATE tester, anticipating the scaling demands of AI/ML datacenter products (~$1.4B portfolio). Partnered with HW/SW engineering, CM, vendors, and supply chain teams to deliver a first-of-kind tester platform deployed globally across offshore factories to secure future product readiness.
- Collaborated with cross-functional teams to propose and evaluate new manufacturing capabilities, including –55C Start-of-Test for a $500M military program. Assessed advanced cooling options (HFE/EGDI chillers with TEC optimization), process tolerances, and product-level trade-offs to shape ATE tester and long-term equipment readiness.
- Led cross-functional team of 12 (HW/SW/operations) to develop and deploy scalable HTOL product qualification processes for AI/ML silicon. Translated complex industry standards into production-ready flows across offshore factories, extending stress test capability 50x (10hrs to 500hrs) and reducing yield loss 3x, accelerating qualification schedules by nearly a quarter.
- Collaborated with key suppliers (Cisco, Fidus) to address manufacturing quality challenges, leading joint root-cause investigations and corrective actions. Recovered up to 8% yield while strengthening supplier engagement and long-term manufacturing reliability.
- Led the investigation, qualification, and production deployment of Thicker Interposer technology for tester hardware, driving the concept from proposal through manufacturing adoption. Partnered with cross-functional and supplier teams to enable higher parallelism (x12 -> x16), improving test coverage by 10% and freeing 25% factory capacity, delivering efficiency gains across a $650M server product portfolio.
- Led and mentored a 4-member TP/Software team in developing and validating the Time to Resume (TTR) software feature for burn-in test flow. This innovation, driven from concept to production, prevented 4% yield loss and delivered $20M in quarterly savings, ultimately becoming a process-of-record (POR) across all Intel products.
- Partnered with HW/SW and manufacturing teams to invent and deploy Multiple Burn-In Time (MBIT) unit grouping technology in production flows. Originally conceived to resolve a critical throughput bottleneck, MBIT enabled more efficient tool utilization—saving the equivalent of half a burn-in tool per product—and improved throughput by 7–20%, delivering multi-million-dollar annual savings.
- Introduced automation into the burn-in flow by enabling handlers to pick and place units into sockets, eliminating manual socketing for HTOL milestones. Directed cross-functional teams to implement this first-of-kind Long Test Time (LTT) capability, reducing lot handling time from 21 hours to 14 hours. This innovation improved manufacturing efficiency delivered $120K in equipment savings, and eliminated the need for four shifts of additional headcount.
- Led the qualification and production deployment of Elastomer socket technology, introducing a new approach to improve contact reliability in tester hardware. Partnered with suppliers and cross-functional teams to validate the solution, reducing retest rates from ~3.5% to
- Led cross-functional debug across design, product, and test teams to resolve a critical PLL instability spanning burn-in platform, IP design, and test program interactions. Applied structured problem-solving to identify root cause in TP instability, enabling a fix that recovered ~28% yield and removed a PRQ showstopper for high-value Intel silicon.
- Partnered with silicon and test teams to resolve thermal runaway and overcurrent issues by analyzing test content interactions with leakage and PLL frequency. Strengthened power and thermal reliability in production, improving efficiency and recovering ~5% yield.
- Led software team in addressing a Pattern Generator FPGA instability that caused yield loss in production testing. Improved test program robustness and safeguarded ~3% yield, ensuring stable high-volume manufacturing.
- Directed resolution of Power Supply Distribution Board (PSDB) reliability issue by coordinating FPGA-driven software upgrades. Improved test hardware stability and reduced retest rates by 7%, enhancing overall manufacturing efficiency.
- Additional Experience at INTEL Corp:
- Sr. Product Development Engineer
- June 2015 — April 2017
- Directed development and deployment of ATE/SLT test programs and silicon characterization flows for flagship Intel products, ensuring smooth NPI and high-volume manufacturing readiness. Collaborated across design, product, and factory teams to validate integration, resolve yield challenges, and safeguard reliability of advanced packaging technologies.
- Software Validation Engineer
- June 2013 — May 2015
- Owned the validation of Tester Operating System (TOS) software building blocks through requirement gathering, design, coding and testing for manufacturing release. Facilitated Scrum frameworks for multiple projects, ensuring timely delivery, and fostering collaborative environments that encouraged active participation and continuous improvements.
- Test R&D Engineer in System Test
- October 2010 — May 2013
- Led the development of innovative testing methodologies to improve SLT cost efficiency. Accounted for formulating scalable and cost-effective testing solutions for factory implementation.
- Led technology integration projects, enhancing operational efficiency across various departments.
Education
Ph.D. - Electrical & Computer Engineering (Design for Test)
Southern Illinois University
Carbondale, IL08.2011
Skills
- ATE & SLT Test Hardware Development
- Silicon Qualification & Manufacturing Readiness
- Process Development & NPI
- Technical Leadership & Innovation Deployment
- Advanced Excel/Power BI/JMP for data analysis
- Risk Assessment & Problem Solving
- Cross-Functional & Vendor Collaboration
- Yield Recovery & Efficiency Improvements
- Testability, Reliability & DFT/DFM
Timeline
Test Technologist/TPM
INTEL Corp.
05.2017 - 07.2025
Ph.D. - Electrical & Computer Engineering (Design for Test)
Southern Illinois University
Awards & Honors
Foundry TD Excellence Award for “Enabling Elastomer Test Socket Technology for Improved Test Coverage, Stability, and Cost”. – 2024., Received Manufacturing Platform Enabling (Customer) Divisional Recognition Award for driving the enablement of FOK Long Test Time (LTT) capability on Burn-In Test platform to support product ELT/HTOL milestones with 75% execution time improvement, $120K in lifter savings, and 4 shift head count avoidance - 2024., Received Manufacturing Platform Enabling (Customer) TD Excellence Award in 2023 for implementing HBI in-situ MBIT Unit-Grouping, saving 0.5 binning tool per product family and improving throughput by 7%-20%., Recipient of the Technology Development Excellence Award in 2022 for the breakthrough manufacturing Burn-in platform development to replace end of life LCBI platform with reduced hardware cost and keeping the same parallelism., Recipient of TPTD Q4’ 2021 Department Award leading successful cross-functional team to release 19 PSDB hardware from quarantine, resolving 7% product retest rate., Recipient of STTD Department Award 2018 resolving the product yield loss issue, achieving ~4% retest savings., Honored with STTD department award in 2015 for achieving the fastest time to production for Intel’s phone product, leading to ~$10 million in capital avoidance.
Publications
- “Expanding HDBI Stress Capability Envelope for Intel IDM2.0 Product Qualification” Intel Assembly & Test Technology Journal, Vol. 27, 2024
- “Minimizing Observation Points for Fault Location”, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
- “LFSR Reseeding with Irreducible Polynomials”, 13th IEEE International On-Line Testing Symposium (IOLTS 2007)