Expertise in processor design demonstrated through FPGA-based implementation of a full-scale pipelined datapath, focusing on hardware, software, and instruction set architecture tradeoffs. Successfully designed and validated a five-stage pipelined datapath for MIPS 32-bit ISA on Xilinx Artix-7 FPGA. Developed and executed a video processing algorithm in MIPS ISA on FPGA-based emulation, showcasing practical application of theoretical knowledge.
PACT Online Cyber Security Certification, 06/01/2023